53,209 research outputs found
Integrating 'atomistic', intrinsic parameter fluctuations into compact model circuit analysis
MOSFET parameter fluctuations, resulting from the 'atomistic' granular nature of matter, are predicted to be a critical roadblock to the scaling of devices in future electronic systems. A methodology is presented which allows compact model based circuit analysis tools to exploit the results of 'atomistic' device simulation, allowing investigation of the effects of such fluctuations on circuits and systems. The methodology is applied to a CMOS inverter, ring oscillator, and analogue NMOS current mirror as simple initial examples of its efficacy
Breakdown of universal mobility curves in sub-100-nm MOSFETs
We explore the breakdown of universal mobility behavior in sub-100-nm Si MOSFETs, using a novel three-dimensional (3-D) statistical simulation approach. In this approach, carrier trajectories in the bulk are treated via 3-D Brownian dynamics, while the carrier-interface roughness scattering is treated using a novel empirical model
RF analysis methodology for Si and SiGe FETs based on transient Monte Carlo simulation
A comprehensive analysis methodology allowing investigation of the RF performance of Si and strained Si:SiGe MOSFETs is presented. It is based on transient ensemble Monte Carlo simulation which correctly describes device transport, and employs a finite element solver to account for complex device geometries. Transfer characteristics and figures of merit for a number of existing and proposed RF MOSFETs are discussed
The impact of random doping effects on CMOS SRAM cell
The SRAM has a very constrained cell area and is consequently sensitive to the intrinsic parameter fluctuations ubiquitous in decananometer scale MOSFETs. Using a statistical circuit simulation methodology, which can fully collate intrinsic parameter fluctuation information into compact model sets, the impact of random device doping on 6-T SRAM static noise margins, and read and write characteristics are investigated in detail for well-scaled 35 nm physical gate length devices. We conclude that intrinsic parameter fluctuations will become a major limitation to further conventional MOSFET SRAM scaling
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Strategies for successful field deployment in a resource-poor region: Arsenic remediation technology for drinking water
Strong long-term international partnership in science, technology, finance and policy is critical for sustainable field experiments leading to successful commercial deployment of novel technology at community-scale. Although technologies already exist that can remediate arsenic in groundwater, most are too expensive or too complicated to operate on a sustained basis in resource-poor communities with the low technical skill common in rural South Asia. To address this specific problem, researchers at University of California-Berkeley (UCB) and Lawrence Berkeley National Laboratory (LBNL) invented a technology in 2006 called electrochemical arsenic remediation (ECAR). Since 2010, researchers at UCB and LBNL have collaborated with Global Change Program of Jadavpur University (GCP-JU) in West Bengal, India for its social embedding alongside a local private industry group, and with financial support from the Indo-US Technology Forum (IUSSTF) over 2012â2017. During the first 10 months of pilot plant operation (April 2016 to January 2017) a total of 540 m3 (540,000 L) of arsenic-safe water was produced, consistently and reliably reducing arsenic concentrations from initial 252 ± 29 to final 2.9 ± 1 parts per billion (ppb). This paper presents the critical strategies in taking a technology from a lab in the USA to the field in India for commercialization to address the technical, socio-economic, and political aspects of the arsenic public health crisis while targeting several sustainable development goals (SDGs). The lessons learned highlight the significance of designing a technology contextually, bridging the knowledge divide, supporting local livelihoods, and complying with local regulations within a defined Critical Effort Zone period with financial support from an insightful funding source focused on maturing inventions and turning them into novel technologies for commercial scale-up. Along the way, building trust with the community through repetitive direct interactions, and communication by the scientists, proved vital for bridging the technology-society gap at a critical stage of technology deployment. The information presented here fills a knowledge gap regarding successful case studies in which the arsenic remediation technology obtains social acceptance and sustains technical performance over time, while operating with financial viability
Parallel semiconductor device simulation: from power to 'atomistic' devices
This paper discusses various aspects of the parallel simulation of semiconductor devices on mesh connected MIMD platforms with distributed memory and a message passing programming paradigm. We describe the spatial domain decomposition approach adopted in the simulation of various devices, the generation of structured topologically rectangular 2D and 3D finite element grids and the optimisation of their partitioning using simulated annealing techniques. The development of efficient and scalable parallel solvers is a central issue of parallel simulations and the design of parallel SOR, conjugate gradient and multigrid solvers is discussed. The domain decomposition approach is illustrated in examples ranging from `atomistic' simulation of decanano MOSFETs to simulation of power IGBTs rated for 1000 V
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