53,209 research outputs found

    Integrating 'atomistic', intrinsic parameter fluctuations into compact model circuit analysis

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    MOSFET parameter fluctuations, resulting from the 'atomistic' granular nature of matter, are predicted to be a critical roadblock to the scaling of devices in future electronic systems. A methodology is presented which allows compact model based circuit analysis tools to exploit the results of 'atomistic' device simulation, allowing investigation of the effects of such fluctuations on circuits and systems. The methodology is applied to a CMOS inverter, ring oscillator, and analogue NMOS current mirror as simple initial examples of its efficacy

    Breakdown of universal mobility curves in sub-100-nm MOSFETs

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    We explore the breakdown of universal mobility behavior in sub-100-nm Si MOSFETs, using a novel three-dimensional (3-D) statistical simulation approach. In this approach, carrier trajectories in the bulk are treated via 3-D Brownian dynamics, while the carrier-interface roughness scattering is treated using a novel empirical model

    RF analysis methodology for Si and SiGe FETs based on transient Monte Carlo simulation

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    A comprehensive analysis methodology allowing investigation of the RF performance of Si and strained Si:SiGe MOSFETs is presented. It is based on transient ensemble Monte Carlo simulation which correctly describes device transport, and employs a finite element solver to account for complex device geometries. Transfer characteristics and figures of merit for a number of existing and proposed RF MOSFETs are discussed

    The impact of random doping effects on CMOS SRAM cell

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    The SRAM has a very constrained cell area and is consequently sensitive to the intrinsic parameter fluctuations ubiquitous in decananometer scale MOSFETs. Using a statistical circuit simulation methodology, which can fully collate intrinsic parameter fluctuation information into compact model sets, the impact of random device doping on 6-T SRAM static noise margins, and read and write characteristics are investigated in detail for well-scaled 35 nm physical gate length devices. We conclude that intrinsic parameter fluctuations will become a major limitation to further conventional MOSFET SRAM scaling

    Parallel semiconductor device simulation: from power to 'atomistic' devices

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    This paper discusses various aspects of the parallel simulation of semiconductor devices on mesh connected MIMD platforms with distributed memory and a message passing programming paradigm. We describe the spatial domain decomposition approach adopted in the simulation of various devices, the generation of structured topologically rectangular 2D and 3D finite element grids and the optimisation of their partitioning using simulated annealing techniques. The development of efficient and scalable parallel solvers is a central issue of parallel simulations and the design of parallel SOR, conjugate gradient and multigrid solvers is discussed. The domain decomposition approach is illustrated in examples ranging from `atomistic' simulation of decanano MOSFETs to simulation of power IGBTs rated for 1000 V
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